TSMC said A13 reflects the company’s continued commitment to innovation. Compared with A14, A13 reduces chip area by 6%, and its design rules are fully backward-compatible with A14, enabling customers to quickly migrate their designs to TSMC’s latest nanosheet transistor technology. Through design-technology co-optimization (DTCO), A13 also provides additional gains in power efficiency and performance. A13 is expected to enter production in 2029, one year after A14 reaches mass production.
A13 was one of the headline technology announcements made at TSMC’s North America Technology Symposium in Santa Clara, California, which also marked the start of the company’s global technology forum series in the coming months. Held under the theme “Expanding AI with Leadership Silicon,” the 2026 symposium is TSMC’s largest customer event of the year and offers a comprehensive showcase of the company’s latest technology developments and manufacturing services.
TSMC Chairman and CEO C.C. Wei said, “TSMC’s customers are always looking ahead to future innovations. They expect us to continue delivering dependable new technologies such as A13, and they want those carefully developed technologies to be ready for volume production exactly when their forward-looking new designs require them. TSMC’s advanced process technologies lead the industry in density, performance, and power efficiency, but we continue to look for ways to optimize them further to better support our customers’ future products. As our customers’ most trusted technology partner, we are fully committed to enabling their success.”
Other new technologies announced at the North America Technology Symposium include:
• In addition to A13, TSMC further enhanced its A14 platform and previewed its A12 technology. A12 will adopt TSMC’s Super Power Rail technology to deliver backside power for AI and high-performance computing applications and is expected to enter production in 2029.
• TSMC is also advancing its N2 platform with the introduction of N2U. Enabled by design-technology co-optimization, N2U delivers 3% to 4% higher speed or 8% to 10% lower power consumption than N2P, along with 2% to 3% higher logic density. Built on the process maturity and strong yield performance of the N2 technology platform, N2U is positioned as a well-balanced option for AI, high-performance computing, and mobile applications. N2U is expected to enter production in 2028.
TSMC 3DFabric advanced packaging and 3D silicon stacking:
• To address AI’s demand for greater compute and memory capacity within a single package, TSMC continues to expand its CoWoS technology to integrate more dies. TSMC is currently manufacturing 5.5-reticle-size CoWoS and is planning even larger versions. A 14-reticle-size CoWoS solution will be able to integrate approximately 10 large compute chiplets and 20 high-bandwidth memory (HBM) stacks and is expected to begin production in 2028.
TSMC will then introduce a CoWoS solution larger than 14 reticle sizes in 2029. These new technologies will give customers more options to scale AI computing performance and will complement TSMC’s System-on-Wafer-X (SoW-X) technology at 40 reticle sizes, which is also expected to launch in 2029.
• TSMC will also introduce its System on Integrated Chips (TSMC-SoIC) 3D chip stacking technology on its most advanced technology platforms. A14 with A14 SoIC is expected to enter production in 2029, offering die-to-die I/O density 1.8 times higher than N2 with N2 SoIC technology, enabling greater data transmission bandwidth between stacked chips.
• TSMC’s Compact Universal Photonic Engine (TSMC-COUPE™) is set to reach a major milestone. A true co-packaged optics (CPO) solution using COUPE on substrate is expected to enter production in 2026.
Compared with pluggable solutions on a motherboard, this new technology integrates the COUPE photonic engine directly inside the package, delivering twice the energy efficiency and reducing latency by 90%. The technology is already being applied to a 200Gbps micro-ring modulator (MRM), providing a highly streamlined and energy-efficient solution for data transmission between data center racks.