According to Commercial Times, TSMC began delivering equipment to its R&D teams in February for its CoPoS (Chip-on-Panel-on-Substrate) pilot production line. The full line is expected to be completed by June.
The report notes that the rise of CoPoS highlights the industry’s shift toward panel-level packaging as a potential solution to advanced packaging bottlenecks. As AI chip reticle sizes continue to grow—such as NVIDIA’s Rubin GPU, which is reportedly 5.5 times larger than previous designs—a standard 12-inch wafer can now accommodate only seven units, or in some cases as few as four. Panel-based square formats are expected to significantly improve utilization and throughput, with the long-term goal of replacing silicon interposers with glass substrates.
With TSMC’s CoPoS pilot line expected to be completed by mid-year, the industry generally anticipates volume production to ramp up between 2028 and 2029. However, supply chain sources cited in the report caution that as substrate sizes increase, warpage issues also become more severe, posing a major challenge for large-scale manufacturing.
TSMC may also establish its first CoPoS pilot line in Chiayi and plans to use the site for future mass production. The company is further expected to integrate CoPoS with its SoIC (System on Integrated Chips) and WMCM (Wafer-Level Multi-Chip Module) technologies.
In addition, TSMC plans to convert its existing 8-inch wafer fabs in Taiwan into advanced packaging facilities, while its current back-end fabs will support production for leading-edge 2nm processes.