This new device was funded by the U.S. Air Force Research Laboratory (AFRL) Space Vehicles Directorate and co-developed with Microelectronics Research Development Corporation (Micro-RDC). It is based on Infineon's proven SONOS (Silicon Substrate-Subthreshold Oxide Layer-Charge Trapping Nitride Oxide Layer-Polycrystalline Gate) charge trap technology, offering up to 30% higher operating speed compared to lower-density alternatives.
Richard Marquez, AFRL's Space Electronics Technology Program Manager, stated: "Designers of next-generation space systems are increasingly demanding highly reliable, high-density memory. Our collaboration with industry leaders like Infineon and Micro-RDC has led to the development of a solution that combines high density, high data transfer rates, and superior radiation performance compared to alternative technologies."
Joseph Cuchiaro, President of Micro-RDC, commented: "Infineon's radiation-hardened NOR flash memory complements Micro-RDC's extreme environment solutions. With the introduction of the 512 Mbit density device, designers can now build high-performance systems to meet the rigorous demands of a broader range of mission types than ever before."
Helmut Puchner, Vice President of Infineon's Aerospace & Defense Business, said: "The expansion of the Infineon 512 Mbit NOR flash family to include radiation-hardened memory further demonstrates our commitment to providing highly reliable, high-performance memory solutions for next-generation space requirements. Our collaboration with AFRL and Micro-RDC advances industry-leading technology, using solutions that improve key satellite functionality to address the extreme environments encountered in space applications."
Infineon's SONOS technology uniquely combines density and speed with advanced radiation performance, offering an excellent durability of up to 10,000 P/E cycles and a 10-year data retention period. The 133 MHz QSPI interface provides high data transfer rates for space-grade FPGAs and processors. It is available in two packages: a ceramic QFP (QML-V) with a board area of 1" x 1" and a smaller 0.5" x 0.8" plastic TQFP (QML-P) package. Additionally, the device provides the highest density TID/SEE performance combination for space FPGA boot code solutions. Its QML-V/P package has been DLAM certified and meets the most stringent industry qualification requirements.
Typical use cases for this device include storage of configuration images for space-grade FPGAs and independent boot code storage for space-grade multi-core processors.