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Breakthrough in packaging technology, TSMC, Intel lead OEM inspection and testing plant

For HPC chip packaging technology, TSMC has proposed a new state-of-the-art SoIC (SystemonIntegratedChips) 3D packaging technology paper in the VLSI Technology and Circuits Symposium (2019SymposiaonVLSITechnologies & Circuits) in June 2019; through the density of bumping bumps, Improve the overall speed of operation between the CPU/GPU processor and the memory.

Overall, it is expected to continue to extend through SoIC packaging technology, and as a new solution for TSMC's advanced packaging in the back-end of InFO (Integrated Fan-out) and CoWoS (Chipon Waferon Substrate).

3D packaging successfully improves HPC productivity with vertical stacking and miniature volume methods

Due to the breakthrough of semiconductor development technology and the shrinking of component size, the development of HPC chip packaging must consider the volume required for packaging and the improvement of chip performance. Therefore, the future development trend of HPC chip packaging technology is in addition to the existing fan-out type. In addition to the wafer-level package (FOWLP) and 2.5D package, the development of the more difficult 3D packaging technology will be the goal.

The so-called 3D packaging technology is mainly to improve the computing speed and capability of AI's HPC chip, trying to integrate HBM high-bandwidth memory and CPU/GPU/FPGA/NPU processors with high-end TSV (Siliary Perforation) technology. At the same time, the two are vertically stacked together to reduce each other's transmission path, speed up processing and operation speed, and improve the working efficiency of the overall HPC chip.

TSMC and Intel are actively introducing 3D packaging, which will lead the OEM packaging and testing plant to follow up

According to the current 3D packaging technology, since the processor and the memory in the HPC chip must be vertically stacked, the development cost is much higher than the other two package technologies (FOWLP, 2.5D package), and the process difficulty is more complicated. The finished product yield is low.

At present, the latest achievements of 3D packaging technology have been announced. At this stage, in addition to the semiconductor OEM manufacturing leader, TSMC is the most active. It has announced that it is expected to introduce 3D packaging technologies such as SoIC and WoW (WaferonWafer) in 2020, and IDM OEM Intel. It also proposes the 3D packaging concept of Foveros, which will face the packaging market of subsequent processors and HPC chips in the second half of 2019.

As semiconductor foundry manufacturers and IDM plants continue to invest in R&D resources for 3D packaging technology, they will also lead another wave of 3D packaging and testing technology. It is believed that OEM packaging and testing factories (such as ASE, Amkor, etc.) will also step up their efforts. The development trend of this wave 3D packaging technology.